Ethernet Standards
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Data Center Infrastructure
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1.6T Ethernet in the Data Center
Learn why Ethernet speeds will reach 1.6 terabits per second and what leaders in the networking industry are saying about the innovations required to enable it. (47 min)
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Evaluating Electrical Performance in Electrical-Optical-Electrical Link Systems
In this webinar, we examine a design approach for E-O-E systems that predicts design margin, such as eye height and eye width, at the desired system bit error rate.
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Signal Integrity
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Designing for Signal Integrity
Learn the 3-step approach to solve Signal Integrity problems (10 min)
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Designing a Robust Workflow for Signal Integrity
Learn about insights into the mechanisms that affect signal integrity and some practical tips for evaluating link designs and troubleshooting issues.
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Finding & Solving Signal Integrity Issues
Learn how to find and solve signal integrity problems in a high-speed digital communications channel. (30 min)
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Power Integrity
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How to Design for Power Integrity
Steve Sandler provides a solid foundation for designing Power Delivery Networks and tips and tricks to avoid design pitfalls (60 min)
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Power Integrity Simulation & Measurement Skills
Learn the importance of power integrity, how to simulate for optimal power design, and how to measure a system's power performance. (40 min)
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Designing Power Integrity Power Distribution Networks
Join Heidi Barnes to learn about how to design Power Integrity Power Distribution Networks.
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Optimizing Capacitor Selection and Placement for Power Integrity
Gain insights on power integrity simulation methods in PathWave ADS with PIPro that will simplify the selection and placement of capacitors on a power distribution network.
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DDR Memory
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Introduction to DDR4 and DDR5 memory
Listen in as DDR expert Perry Keller provides an overview of DDR4 and what to expect with DDR5. (45 min)
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Quick Start to DDR5 Memory Design
Get a quick start on the new challenges with DDR5, and strategies for how to build a new Design-to-Test workflow for DDR5 (30 min)
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Analyzing Memory Bus to Meet with DDR Specifications
Learn the importance of memory channel pre- and post-layout models, how to build them, and how to design with them.
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Overcoming DDR challenges with DRAM AMI modeling
Overcome DDR5 design challenges with DRAM AMI modeling tools.
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DDR5 Simulation with Memory Designer
Learn how to approach a workflow for Memory interfaces and Memory hardware designs. (10 min)
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USB
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Keysight Talks Standards: USB4
Jit Lim provides an overview of USB4. Hear about what you need to consider when testing, debugging, and characterizing your USB4 designs.
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